In Published Japanese translation of PCT application No. 2005-537597, a flash memory device which employs the MirrorBit (registered trade mark) architecture is disclosed. In the MirrorBit architecture, two bits can be stored per memory cell. For reading out a memory cell, two column lines adjacent to the memory cell and auxiliary two column lines located outside of said two column lines are selected. One of the two column lines is connected to ground and the other one is connected to a voltage source to provide basic sensing current for the memory cell. Also, the auxiliary two column lines are respectively connected to ground and the voltage source to reduce error current. In this manner, four column lines are selected. Such column line selection is carried out by a diffusion bit line selection unit of a four-column Y-decoder and a metal bit line selection unit of the four-column Y-decoder. The connection points of column lines are selected by a source selector.
In a burst operation to sequentially access adjacent memory cells, when using an access method of four-column selection, an additional column line must be selected for a newly accessed memory cell. Also, a connection point of a column line common with the preceding memory cell and the newly accessed memory cell needs switching between a ground potential and a voltage source. Thus, at least one switching element must be operated in the diffusion bit line selection unit and in the metal bit line selection unit. Further, at least one switching element must be operated in the source selector. Therefore, two or more switching elements must be performed in total.
However, in the burst operation, there occurs a non-sequential access operation, such as accessing from a memory cell located at one end to a memory cell located at the other end of a block as one unit for a sequential access operation. In this time, the four line column selection access method requires selection of two additional column lines as well as two auxiliary column lines. Thus, at least four switching elements must be operated in the diffusion bit line selection unit, the metal bit line selection unit, and the source selector. This means that the number of switching elements varies between in a sequential access operation and in a non-sequential access operation. Therefore, load capacity of circuits such as the diffusion bit line selection unit, the metal bit line selection unit, and the source selector varies in accordance with transition of column address.
For the above-described reason, circuits such as the diffusion bit line selection unit were conventionally operated based on the load capacity required during a non-sequential access operation which accompanies the largest load. Consequently, driving ability during the sequential access operation with less load capacity becomes redundant, leading to increase in consumption current. Also, during a sequential access operation, excessively boosted voltage needs regulating into a predetermined voltage so that regulating time increases and hence access time increases.